Recently, there has been a demand for a system large scale integrated circuit (LSI) that combines several LSIs into a single LSI. The demand has been driven by the desire for more compact and faster devices and products. Further, a hybrid LSI, combining an analog circuit and a digital circuit into a single LSI has been developed as communications technology progresses.
A capacitor having a highly precise and stable characteristics independent of voltage is required for the manufacture of analog circuits. Polysilicon insulator polysilicon (PIP) capacitors have been used in such applications. The PIP capacitor is composed of two impurity-doped electrodes and an ONO (oxide-nitride-oxide) film interposed therebetween.
The PIP capacitor has significant drawbacks in that PIP capacitor has large voltage and temperature coefficients, so that the capacitor suffers from a large voltage and temperature dependency. Further, the LSI may not be operated stably due to a large resistance of poly-Si.
As an alternative to solve such problems, therefore, the use of a metal insulator metal (MIM) capacitor has been proposed. The MIM capacitor, utilizing metal electrodes having a lower voltage coefficient and a lower electric resistance than poly-Si, can be formed in multiple wiring layers so that a parasitic capacitance can be also restrained. Particularly, such MIM capacitor is used in a high frequency semiconductor device. That is, a high-frequency device uses the MIM capacitor utilizing a metal of excellent electric characteristics because device characteristics thereof can be changed by RC delay.
FIGS. 1A, 1B, 1C and 1D are cross sectional views showing a structure of a known MIM capacitor and a known manufacturing process. As shown in FIG. 1A, a lower metal layer 102, an insulating layer 104 and an upper metal layer 106 are sequentially deposited on a semiconductor substrate 100. Subsequently, a first photoresist pattern 108 is formed on the upper metal layer 106. The lower metal layer 102 is typically formed by laminating an insulating film such as an oxide film, a Ti/TiN film serving as a first barrier metal film, a metal film made of aluminum or copper, and a Ti/TiN film serving as a second barrier metal film.
Next, an upper electrode film 106′ and a capacitor insulating film 104′ are formed by etching the upper metal layer 106 and the insulating layer 104, as shown in FIG. 1B, wherein the first photoresist pattern 108 and the lower metal layer 102 serve as a mask and an end point, respectively. Conventionally, etching of the upper metal layer 106 and the insulating layer 104 is done by metal RIE.
In a RIE process for etching the upper metal layer 106 and the insulating layer 104, polymer 110 is normally produced on the lower metal layer 102. Though a cleaning process is performed to remove the polymer 110 before performing next processes, the polymer 110 is not removed completely and a part thereof remains.
Next, as shown in FIG. 1C, the first photoresist pattern 108 is removed and then there is formed on the resultant structure a second photoresist pattern 112 for completely encapsulating the upper electrode film 106′ and the capacitor insulating film 104′ to pattern the lower metal layer 102.
Subsequently, as shown in FIG. 1D, a lower electrode film 102′ is formed by etching the lower metal layer 102 by using the second photoresist pattern 112 as a mask, and then the second photoresist pattern 112 is removed. Therefore, a MIM capacitor 114 including the lower electrode film 102′, the capacitor insulating film 104′ and the upper electrode film 106′ is obtained.
However, certain parts of the lower metal layer 102, e.g., an area shown in FIG. 1D at reference character A, may not be properly etched at the step of etching the lower metal layer 102 due to the polymer 110 remaining on the lower metal layer 102. Therefore, characteristics of the MIM capacitor are deteriorated and a production yield is also lowered.